1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a trench-gate semiconductor device.
2. Description of the Related Art
Known power semiconductor elements capable of achieving a low on resistance include a trench-gate MOS transistor and an insulated-gate bipolar transistor (IGBT).
A trench-gate, n-channel MOS transistor, for example, includes trenches formed in stripes or mesh such that they extend from an n-type source layer through a p-type base layer located below the source layer. A film of conductor such as polysilicon is buried with a gate insulator on a trench wall to form a gate electrode. Such the structure produces a power semiconductor element with a lower on resistance than that of the so-called planar gate type that includes a gate electrode formed on a gate insulator formed over a surface of the base layer.
In such the trench-gate structure, electric field concentration may easily arise at a corner of the bottom of the trench and this may cause deterioration of the breakdown voltage as a problem. When the trench width is reduced as fine patterning proceeds, the radius of curvature at the trench corner further decreases, and the degree of electric field concentration increases at the trench corner of the trench bottom. If the radius of curvature at the trench corner is small, current flows in a drift layer not uniformly, thereby increasing the drift resistance, resulting in increases in on resistance and power consumption in the element as a problem. Therefore, an anisotropic etching is applied to the trench bottom to round the trench bottom to form an almost reverse-tapered (flask-shaped) trench having an enlarged radius of curvature (see JP2001/244325A, paragraphs 0019-0022, FIG. 1 and so forth). This shape relieves the electric field at the trench bottom to improve the breakdown voltage and enables the drift layer to be thinned to the extent to reduce the drift resistance and thus reduce the on resistance.
When such the reverse-tapered trench is formed, a void may easily arise in the conductor film, or polysilicon film, configuring the gate electrode. The void causes no problem so long as it exists in the polysilicon film at the center. Rather, it reduces stresses due to fine pattering and contributes to prevention of occurrences of D-S leakage current. During crystallization of polysilicon proceeding in a heat treatment step executed after the formation of polysilicon, however, the void may migrate and come into contact with the gate insulator possibly. In this case, in the p-type base layer opposite to the void brought into contact with the gate insulator, an inverted layer is hardly formed even though the gate voltage is applied. In addition, in the drift layer below the base layer, an accumulation layer is hardly formed. Accordingly, this causes an increase in on resistance as a problem. The void easily occurs in the reverse-tapered trench though the same problem arises if a void occurs regardless of the trench shape.
Such the migration of the void may cause the following two problems associated with the reliability of the gate electrode. One is a problem found in a gate ruggedness test because an electric field concentrates on the gate insulator at a void edge (a boundary between the void and the polysilicon). Accordingly, the breakdown ruggedness lowers and reduces TDDB and ESD ruggedness. Another is a problem related to the above electric field concentration that facilitates charges to flow through the gate insulator. This causes a threshold voltage fluctuation due to a charge trap in the insulator in a high-temperature gate bias test.